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INTEGRATED CIRCUITS
DATA SHEET
SAA4700T VPS dataline processor
Preliminary specification File under Integrated Circuits, IC02 March 1991
Philips Semiconductors
Preliminary specification
VPS dataline processor
SAA4700T
FEATURES * Adaptive sync slicer with buffered composite sync output VCS * Adaptive data slicer * Data rate clock regenerator * Field selection and line 16 decoding * Startcode and biphase check * Data valid output * Storage of data line information in a 40 bit register bank * I2C-bus transmission
GENERAL DESCRIPTION The SAA4700T is a bipolar integrated circuit designed for use in dataline receivers and incorporates a dataline slicer and decoder. The slicer extracts the dataline signal from the video signal and regenerates the data clock. It also provides signals for the decoder in order to decode the binary data that is transmitted in line 16 of every first field of the composite video signal (video programming signal and video recording programming by Teletext, VPS and VPT systems). The decoded information out of words 5 and 11 to 14 is accessed via the built-in I2C-bus interface. This information then can be used for programming a video cassette recorder in order to start and stop a recording of a television program at the correct aligned time, regardless of a delay or extension in the transmission time of the required program.
QUICK REFERENCE DATA SYMBOL VP IP Vi CVBS Tamb PARAMETER supply voltage (pins 17 and 18) total supply current CVBS input signal sync-to-white (peak-to-peak value) operating ambient temperature - 0.5 0 MIN. 4.5 5 18 1 - TYP. MAX. 5.5 23 1.4 +70 V mA V C UNIT
ORDERING AND PACKAGE INFORMATION EXTENDED TYPE NUMBER SAA4700T Note 1. SOT163-1; 1996 November 13. 20 PACKAGE PINS PIN POSITION mini-pack MATERIAL plastic CODE SOT163A (1)
March 1991
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Philips Semiconductors
Preliminary specification
VPS dataline processor
SAA4700T
handbook, full pagewidth
CSO 0.1 F 5 6 (test line 16) 12 FIELD SELECTOR LINE 16 DECODER line 16
DAV AD = LOW 13 OUTPUT CONTROLLER 8 9 I2C-BUS CONTROL SCL SDA
CVBS
4.7 nF
2
SYNC SEPARATOR
10
470 pF
SAA4700T
1 nF
5 8
1
DATA SLICER
data
40 BIT DATA REGISTER data 4
4.7 k
INPUT CONTROLLER
40 BIT DATA LATCH
CLOCK REGENERATOR 75 k (2%) to VP 4.7 nF 22 nF 8.2 k VCS 15 PLL WITH 5 MHz VCO AND PHASE DETECTOR
6
MULTIPLEXER
7 14 20
n.c. n.c. n.c.
19
TIME BASE
REFERENCE VOLTAGES POWER-ON RESET 3 4 17 18
external reset
16
11
clock pulse
0.1 F
+5 V VP
MGH128
Fig.1 Block diagram and test circuit.
FUNCTIONAL DESCRIPTION Dataline 16 The information in dataline 16 consists of fifteen 8-bit words; the total information content is shown in Table 1; and the organization of transmitted bytes is shown in Table 2. Out of the fifteen possible 8-bit words the SAA4700T extracts words 5 and 11 to 14. The contents of these words can be read via the built-in I2C-bus interface. The circuit is fully transparent, thus each bit is transferred without modification with only the sequence of words being changed. Words 11 to 14 are transmitted first followed by word 5. By evaluating the sliced sync signal the circuit can identify the beginning of dataline 16 in the first field. The dataline decoder stage releases the start code detector. When a March 1991 3
correct start code is detected (for timing of start code detection see Fig.3) words 5 and 11 to 14 are decoded, checked for biphase errors and stored in a register bank. If no biphase error has occurred, the contents of the register bank are transferred to a second register bank by the data valid control signal. If the system has been addressed, this transfer will be delayed until the next start or stop condition of the I2C-bus has been received. The last bit of correct information on the dataline remains available until it is read via the I2C-bus. Once the stored information has been read it is considered to be no longer valid and the internal new data flag is reset. Subsequently, if the circuit is addressed, the only VPS data that will be sent back is "FFF to F". The same conditions apply after power-up when no data can be read out. New data is available after reception of another error-free dataline 16.
Philips Semiconductors
Preliminary specification
VPS dataline processor
PINNING SYMBOL CVBS SYNC GND1 GND2 Cblack CSO n.c. AD SCL SDA RS TP DAV n.c. Rosc CP VP1 VP2 Cph n.c. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION video signal input (CVBS from TV) sync amplitude input (CVBS from TV) analog ground (0 V) digital ground (0 V) capacitor for black level composite sync output not connected address set input I2C-bus clock line I2C-bus data line reset input active LOW test point for line 16 decoder data available output active LOW not connected oscillator resistor for frequency adjustment test point clock pulse +5 V supply voltage (digital part) +5 V supply voltage (analog part) capacitor of phase detector not connected CVBS input
GND2 Cblack CSO n.c. AD SCL 4 5
handbook, halfpage
SAA4700T
PIN CONFIGURATION
CVBS SYNC GND1
1 2 3
20 n.c. 19 Cph 18 VP2 17 VP1 16 CP
SAA4700T
6 7 8 9
15 Rosc 14 n.c. 13 DAV 12 TP 11 RS
SDA 10
MBH797
Fig.2 Pin configuration.
External reset The circuit provides an internal power-on reset. When using this facility pin 11 should be connected to VP or, if external reset (RESET = LOW) is to be used pin 11 should be prepared by connecting pin 11 via a 10 k pull-up resistor to VP. Reset forces the following: * I2C-bus not to acknowledge * DAV output to go HIGH (pin 13) * I2C-bus transfer register to "FFF"
The CVBS signal is applied to the sync separator (pin 2) via a decoupling capacitor and to the data slicer (pin 1) via an RC high-pass filter. To enable proper storage of the sync value in the decoupling capacitor, the sync generator output resistance should not exceed 1 k. Black level The capacitor connected to pin 5 stores the black level value for the adaptive sync slicer.
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Philips Semiconductors
Preliminary specification
VPS dataline processor
Composite sync output (CSO) A composite sync output signal for customer application is provided (pin 6). DAV output The data available output pin 13 is set LOW after an error free data line 16 is received. DAV returnes to HIGH after the beginning of the next first field. If no valid data is available DAV remains HIGH. A short duration pulse of 1 s (Fig.5) is inserted at the beginning of dataline 16; it will ensure that a HIGH-to-LOW transmission occurs which can then be used for triggering. Table 1 Information per word in dataline 16 CONTENT run in start code program source identification (binary coded) program source identification (ASCII sequential) sound and VTR control information program/test picture identification internal information exchange address assignment of signal distribution messages/commands 5 MHz VCO and phase detector
SAA4700T
The resistor connected between pin 15 and VP2 determines the current into the voltage controlled oscillator. The RC network connected to pin 19 acts as a low-pass filter for the phase detector. Power supply To prevent crosscoupling the circuit is provided with separate ground and supply pins for analog and digital parts (pins 3, 4, 17 and 18).
WORD NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserve VTR control / information
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Philips Semiconductors
Preliminary specification
VPS dataline processor
Table 2 VTR control information of dataline 16 VTR CONTROL INFORMATION Word number 1 Bit number Label binary Word 5: Bit1 0 0 System status code 1 1 Bit3 1 0 Interrupt code Note 1. address range; NC = nation code; PC = program source code; X = 0 or 1 (bit) Bit2 0 1 0 1 Bit4 0 1 Status 2-channel Mono Stereo 2-channel Status free free 1X00000111111101111111 1X00000111111110111111 1X00000111111111111111 Special system code AD
(1)
SAA4700T
5 8 0
11 7 8
12 15 16
13 23 24
14 31
XXXXXXXX
XXXXXXXX XXXXXXXX Day Month Hour
XXXXXXXX XXXXXXXX Minute Nation Progr. source
NC...NC PC...PC
Pause code
NC...NC PC...PC
NC...NC PC...PC
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Philips Semiconductors
Preliminary specification
VPS dataline processor
SAA4700T
handbook, full pagewidth
0.2 s
clock signal to time base
data to controller run in (word 1) 1 1 error start code pulse 00 01 1 start code (word 2) 01 1 01 1 00 0 11 1 00 0 1 word 3
biphase error pulse (ignored in word 2)
MEH097
Fig.3 Timing diagram of start code detection.
handbook, full pagewidth
white level
0.7 V 1V
0.5 V 5%
sync level 12.5 1.5 s 48 s
MEH098
Fig.4 Timing diagram of dataline 16; modulation depth 71.4%.
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Philips Semiconductors
Preliminary specification
VPS dataline processor
SAA4700T
handbook, full pagewidth
64 s word 10 word 11 word 12 word 13 word 14 word 15 word 1 word 2 word 3 word 4 word 5 word 6 word 7 word 8 48 s word 9 12.5 s
CVBS input
DAV output 1 s line 16 start code pulse word 5 latch pulse word 11 latch pulse word 14 latch pulse
MEH096
Fig.5 Timing diagram of the data available output and word latch pulses.
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Philips Semiconductors
Preliminary specification
VPS dataline processor
LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134). Ground pins 3 and 4 as well as supply pins 17 and 18 tied together. SYMBOL VP1 VP2 Tstg Tamb PARAMETER supply voltage (pin 17) supply voltage (pin 18) storage temperature range operating ambient temperature range -0.5 -0.5 -20 0 MIN.
SAA4700T
MAX. 6.0 6.0 125 +70
UNIT V V C C
THERMAL RESISTANCE SYMBOL Rth j-a PARAMETER from junction to ambient in free air - MIN. MAX. 130 UNIT K/W
CHARACTERISTICS VP1 = VP2 = 5 V; Tamb = 25 C; CVBS signal according to VPS and VPT standard and measurements taken in Fig.1, unless otherwise specified. SYMBOL VP1, VP2 IP Vi CVBS Vi data Vi sync RS VOL VOH IOL IOH td VOL VOH IOL IOH PARAMETER supply voltages (pins 17 and 18) total supply current I17 + I18 sync-to-white note 1; Fig.4 line 16; Fig.4 CONDITIONS - MIN. 4.5 5 18 TYP. MAX. 5.5 23 V mA UNIT
CVBS and sync inputs (pins 1 and 2) CVBS input signal (peak-to-peak value) data input signal (peak-to-peak value, pin 1) sync input signal (peak-to-peak value, pin 2) source resistance 0.5 250 100 - - 2.4 - - - note 2 - 2.4 - - - - - 0.01 0.4 - 500 1 V V A A 1 500 - - - - - - 0.3 1.4 700 600 1 V mV mV k
Composite sync output (pin 6) output voltage LOW output voltage HIGH output current LOW output current HIGH sync separator delay time 0.4 - 200 -500 - V V A A s
DAV output (pin 13) output voltage LOW output voltage HIGH output current LOW output current HIGH
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Philips Semiconductors
Preliminary specification
VPS dataline processor
SAA4700T
SYMBOL
PARAMETER
CONDITIONS - 3 0.9VP IOL = 3 mA - - - - -
MIN. - - - - - - - - - - - - - - -
TYP.
MAX.
UNIT
SCL and SDA (pins 9 and 10) VIL VIH II CI VO ACK tr tf tp L tp H SCL input voltage LOW input voltage HIGH input current input capacitance output voltage during acknowledge on pin 10 rise time fall time pulse duration LOW pulse duration HIGH clock frequency note 2 address 23H address 21H note 2 reset active reset non-active - 2.4 - - 0.4 - -10 1 V V A A 0 2.4 0.4 VP V V 1.5 - 10 10 0.4 1 0.3 - - 100 V V A pF V s s s s kHz
4.7 4.0 -
AD set input (pin 8) VIL VIH VIL VIH IIL IIH Notes input voltage LOW input voltage HIGH
RESET input (pin 11) input voltage LOW input voltage HIGH input current LOW input current HIGH
0.01
1. With standard sync and data amplitude of 68% to 75% black-white. 2. If the open collector output DAV is used, a pull-up resistor to VP1 is necessary.
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Philips Semiconductors
Preliminary specification
VPS dataline processor
SAA4700T
handbook, full pagewidth
VP 22 nF
+5 V 75 k (2%) DAV n.c. 19 18 17 16 15 14 13 12 11
8.2 k n.c. 20
4.7 nF
0.1 F
SAA4700T 1 1 nF 470 pF 2 4.7 nF 3 4 5 0.1 F 6 7 n.c. 8 9 10
4.7 k
CSO
SCL
SDA
CVBS
MEH136
Fig.6 Application circuit.
I2C-BUS FORMAT S SLAVE ADDRESS A DATA A DATA A DATA A DATA A DATA P
S SLAVE ADDRESS A DATA P
= = = = =
start condition 0010 0001 or 0010 0011 for set input AD = HIGH respectively LOW on pin 8 (the circuit is only a slave transmitter) acknowledge, generated by the slave or the master five data bytes, see words in Table 1 stop condition respectively non-acknowledge by the microcontroller
Remarks to I2C-bus transmission * the MSB of each word is transmitted first * there is no restriction on the number of words to be transmitted, but if more than five words are requested, the following content will be "FF" continuously. * Normally every dataline transmission has to be ended with STOP condition by non-acknowledge of the controller.
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Philips Semiconductors
Preliminary specification
VPS dataline processor
PACKAGE OUTLINE SO20: plastic small outline package; 20 leads; body width 7.5 mm
SAA4700T
SOT163-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013AC EIAJ EUROPEAN PROJECTION A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8o 0o
ISSUE DATE 95-01-24 97-05-22
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Philips Semiconductors
Preliminary specification
VPS dataline processor
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
SAA4700T
Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
VPS dataline processor
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA4700T
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
March 1991
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